The increasing operating speeds and computing power of microelectronic devices have recently given rise to the need for an increase in the complexity and functionality of the semiconductor structures from which these devices are fabricated. Hetero-integration of dissimilar semiconductor materials, for example, III-V materials, such as gallium arsenide, gallium nitride, indium aluminum arsenide, and/or germanium with a silicon or silicon-germanium substrate, is an attractive path to increasing the functionality and performance of the CMOS platform. One technique for such integration is often referred to as “heteroepitaxial growth” or “heteroepitaxy,” i.e. epitaxial growth of a semiconductor material over a semiconductor substrate, for example, by chemical vapor deposition (“CVD”) or molecular beam epitaxy (“MBE”), where the semiconductor material, when fully relaxed, has a different lattice constant than the underlying substrate. In particular, heteroepitaxial growth can be advantageously employed to:                (i) fabric ate semiconductor devices for which lattice-matched substrates are not commercially available, e.g. some types of ultra-high speed RF or optoelectronic devices;        (ii) combine multiple new materials on a single wafer, e.g. Ge for p-channel FET devices and InGaAs or InSb for n-channel FET devices;        (iii) improve performance of the conventional CMOS platform by replacing Si, in active areas of some or all transistors on a wafer, with semiconductor materials with higher mobility and saturation velocity than Si, i.e. Ge and/or III-V materials; and        (iv) achieve monolithic integration of semiconductor materials with large mismatch to Si with silicon microelectronics in a manner that is minimally, if at all, disruptive to the CMOS process.        
Depending on the application, key considerations for using selective heteroepitaxy for fabrication of semiconductor devices include:                control of defect density, surface morphology, and degree of relaxation of the desired portions of heteroepitaxial regions;        ease of integration of heteroepitaxy into device manufacturing process; and        reliability of electrical isolation of the defective regions from the active regions of the heterostructure.        
Performance and, ultimately, the utility of devices fabricated using a combination of dissimilar semiconductor materials depend on the quality of the resulting structure. Specifically, a low level of dislocation defects is important in a wide variety of semiconductor devices and processes, because dislocation defects partition an otherwise monolithic crystal structure and introduce unwanted and abrupt changes in electrical and optical properties, which, in turn, results in poor material quality and limited performance. In addition, dislocation defects can degrade physical properties of the device material and can lead to premature device failure.
As mentioned above, dislocation defects typically arise in efforts to epitaxially grow one kind of crystalline material on a substrate of a different kind of material—often referred to as “heterostructure”—due to different crystalline lattice sizes of the two materials. This lattice mismatch between the starting substrate and subsequent layer(s) creates stress during material deposition that generates dislocation defects in the semiconductor structure.
Misfit dislocations form at the mismatched interface to relieve the misfit strain. Many misfit dislocations have vertical components, termed “threading segments,” which terminate at the surface. These threading segments continue through all semiconductor layers subsequently added to the heterostructure. In addition, dislocation defects can arise in the epitaxial growth of the same material as the underlying substrate where the substrate itself contains dislocations. Some of the dislocations replicate as threading dislocations in the epitaxially grown material. Such dislocations in the active regions of semiconductor devices such as diodes, lasers and transistors, may significantly degrade performance.
To reduce formation of dislocations and associated performance issues, many semiconductor heterostructure devices known in the art have been limited to semiconductor layers that have very closely—e.g. within 0.1%—lattice-matched crystal structures. In such devices, a thin layer is epitaxially grown on a mildly lattice-mismatched substrate. As long as the thickness of the epitaxial layer is kept below a critical thickness for defect formation, the substrate acts as a template for growth of the epitaxial layer, which elastically conforms to the substrate template. While lattice-matching (or near matching) eliminate dislocations in a number of structures, there are relatively few known lattice-matched systems, limiting the design options for new devices.
Accordingly, there is considerable interest in heterostructure devices involving greater epitaxial layer thickness and greater lattice misfit than known approaches may allow. For example, it has long been recognized that gallium arsenide grown on silicon substrates may permit a variety of new optoelectronic devices, combining the electronic processing technology of silicon VLSI circuits with the optical component technology available in gallium arsenide. See, for example, Choi et al, “Monolithic Integration of Si MOSFET's and GaAs MESFET's,” IEEE Electron Device Letters, Vol. EDL-7, No. 4, April 1986, incorporated herein by reference. Highly advantageous results of such a combination include high-speed gallium arsenide circuits combined with complex silicon VLSI circuits, and gallium arsenide optoelectronic interface units to replace wire interconnects between silicon VLSI circuits. Progress has been made in integrating gallium arsenide and silicon devices. See, for example, Choi et al, “Monolithic Integration of GaAs/AlGaAs Double-Heterostructure LED's and Si MOSFET's” IEEE Electron Device Letters, Vol. EDL-7, No. 9, September 1986; and Shichijo et al, “Co-Integration of GaAs MESFET and Si CMOS Circuits,” IEEE Electron Device Letters, Vol. 9, No. 9, September 1988, both of which are incorporated herein by reference. However, despite the widely recognized potential advantages of such combined structures and substantial efforts to develop them, their practical utility has been limited by high defect densities in gallium arsenide layers grown on silicon substrates. See, for example, Choi et al, “Monolithic Integration of GaAs/AlGaAs LED and Si Driver Circuit,” IEEE Electron Device Letters, Vol. 9, No. 10, October 1988 (p. 513), incorporated herein by reference. Thus, while basic techniques are known for integrating gallium arsenide and silicon devices, there exists a need for producing gallium arsenide layers having a low density of dislocation defects.
To control dislocation densities in highly-mismatched semiconductor layers, techniques such as wafer bonding and compositional grading have been explored.
Bonding of two different semiconductors may yield satisfactory material quality. Due to the limited availability and high cost of large size Ge or III-V wafers, however, the approach may not be practical.
Compositional grading also may yield satisfactory material quality for some applications, but requires growth of very thick epitaxial layers if substantial lattice mismatch is involved. For example, achieving high quality Ge on Si requires approximately 10 mircons of epitaxial growth. Growing such thick layers may be costly and may also lead to large and deleterious thermal stresses due to differences between the thermal expansion coefficients of the substrate and epitaxial layer. For these reason, compositional grading method may not be practical for many applications.
Another known technique to control dislocations in highly-mismatched semiconductor layers, termed “epitaxial necking” or “aspect ratio trapping,” was demonstrated in connection with fabricating a Ge-on-Si heterostructure by Langdo et al. in “High Quality Ge on Si by Epitaxial Necking,” Applied Physics Letters, Vol. 76, No. 25, April 2000, and also by Park et al. in “Defect reduction of selective Ge epitaxy in trenches on Si (001) substrates using epitaxial necking,” Applied Physics Letters, Vol. 90, 052113, February 2007, both of which are incorporated herein by reference. Relaxation of strain due to mismatched epitaxy can be accomplished by “plastic relaxation,” i.e., relaxation through the nucleation of dislocations 100. The “epitaxial necking” technique focuses on confining these undesirable dislocations to the lower portion of a hole or trench, within a predetermined distance H of the substrate 110-epitaxy interface as shown in FIG. 1a. The semiconductor material grown above a distance H from the substrate can therefore be substantially defect free, and can serve as useful material for the fabrication of a semiconductor device. This approach offers process simplicity by utilizing a combination of selective epitaxial growth and defect crystallography to force defects to the sidewall of the opening in the patterning mask.
Specifically, as shown in FIG. 1b it has been observed experimentally that dislocations in a mismatched cubic semiconductor grown on a Si (100) surface in the near vicinity (e.g., within approximately 500 nm or less) of a vertical dielectric sidewall surface bend toward that surface at approximately 30 degrees through 60 degrees. For example, the dislocations may bend toward that surface at approximately a 45 degree angle to that surface. Based on this relationship, the predetermined distance H necessary to trap a substantial majority of dislocation defects is, typically, approximately equal to a width between ½ w and 2 w, where w is the width of the trench. This range is based on the noted range of intersection angles of approximately 30 degrees through 60 degrees, leading to: tan(30°) w≦H≦tan(60°) w, which roughly corresponds to ½ w≦H≦2 w. Determination of more precise values of H for given semiconductor and substrate combinations, and for given hole or trench dimensions, sidewall materials, and sidewall orientations, is an area requiring more detailed study. For the specific case of Ge grown on (100) Si within trenches oriented along <110> directions with SiO2 sidewalls, H is approximately equal to w (see Park et al., cited above). However, there are limitations to this technique. First, the size of the area for which this technique can successfully trap dislocations is restricted, as noted in the above relation between H and w. This may restrict practical use of epitaxial necking to applications involving relatively small semiconductor devices. Second, the presence of dislocations in the lower portion of the trench or hole may not be acceptable for some device applications, unless a way is found to keep the active regions of a semiconductor device electrically isolated from the dislocations. For some applications, their presence may not be acceptable in any case, and so a means of selective growth that avoids such dislocations (i.e., dislocations associated with plastic relaxation) entirely is highly desirable.
Thus, there is a need in the art for versatile and efficient methods of fabricating semiconductor heterostructures that constrain substrate interface defects in a variety of lattice-mismatched materials systems. There is also a need in the art for semiconductor devices utilizing a combination of integrated lattice-mismatched materials with reduced levels of substrate interface defects for improved functionality and performance.